The present invention relates in general to power field effect transistors (FETs), and in particular to trench-gate FETs with improved characteristics.
FIG. 1 is a simplified cross-section view of a portion of a conventional trench power metal-oxide-semiconductor field-effect transistor (MOSFET). A trench 10 is lined with a gate dielectric 12, and is filled with a conductive material 15, such as polysilicon, which forms the gate of the transistor. The trench extends from the surface of the silicon into the substrate down through a body region 22 and into a drain region 16. Body region 22 is p-type and drain region 16 is n-type. Drain region 16 may be electrically contacted through the substrate (not shown) of the transistor. Source regions 14 are formed adjacent to and on opposite sides of trench 10. An active channel region 20 is thus formed in body region 22 along the trench sidewalls between source regions 14 and drain region 16.
An important parameter in a trench power MOSFET is the total gate charge. In some applications of conventional trench power MOSFETs, such as DC-DC converters, the lower the gate charge the better the efficiency of the overall design. One technique in reducing the gate charge is to reduce the gate to drain capacitance by using a thick dielectric along the bottom of the gate trench. Conventional local oxidation of silicon (LOCOS) processes are used in forming the thick bottom dielectric. A silicon nitride layer is commonly formed along trench sidewalls allowing a thick dielectric to be formed along the trench bottom. However, the anisotropic etch used to remove the portion of the silicon nitride layer along the trench bottom also removes portions of the silicon nitride layer extending over the horizontal surfaces outside the trench.
When forming the thick dielectric along trench bottom, a similarly thick dielectric is formed over the silicon mesa surfaces adjacent to the trench. This thick dielectric over the mesa surfaces causes a number of problems. First, the thick dielectric over the mesa surfaces typically overhangs the upper trench corners, which can cause voiding in the gate polysilicon. Additionally, removing the thick dielectric from over the mesa surfaces requires substantial etching, which can also etch the gate oxide along the upper trench sidewalls. This can lead to gate shorts and yield problems. Also, the variability in the thickness of the dielectric over the mesa surfaces causes variability in the body implant process, which in turn causes variability in the electrical parameters.
Another well-known trench-gate structure is the shielded gate structure. The trench in this structure includes a shield electrode directly below the gate electrode. The shield electrode is insulated from adjacent silicon regions by a shield dielectric which is generally thicker than the gate dielectric. The gate and shield electrodes are insulated from one another by a dielectric layer commonly referred to as inter-poly dielectric or IPD. The IPD is required to be of high quality and to withstand the potential difference between the shield and gate electrodes. One approach in forming the IPD may be to thermally oxidize the shield electrode during the gate oxidation process. However, this approach limits the thickness of the IPD because it is formed at the same time as the gate oxide. Also, the quality of oxide grown on polysilicon is not as good as oxide grown on single crystal silicon. Therefore, it is desirable that the dielectric on the shield polysilicon (the IPD) be much thicker than the gate dielectric so that the IPD can withstand at least as much voltage as the gate dielectric is capable of.
Thus, there is a need for improved techniques for forming the thick dielectric along the trench bottom, and for forming the IPD in shielded gate structures.